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Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Recommended Application: Pin Configuration Frequency Timing Generator for Differential CPU, PCI-Express XIN/CLKIN 1 & SATA clocks Features: * Generates common frequencies from 14.318 MHz or 25 MHz * Crystal or reference input * 8 - 0.7V current-mode differential output pairs * Supports Serial-ATA at 100 MHz * Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread * Unused inputs may be disabled in either driven or Hi-Z state for power management. Key Specifications: * Output cycle-to-cycle jitter < 85 ps * Output to output skew < 85 ps * +/-300 ppm frequency accuracy on output clocks
X2 VDD GND REFOUT FS2 OE_7** DIF_7 DIF_7# VDD DIF_6 DIF_6# OE_6* VDD GND OE_5* DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4** SDATA SCLK
Frequency Select Table SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.66 0 1 1 0 333.33 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.66 1 1 1 0 333.33 1 1 1 1 400.00
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDA GNDA IREF FS0 FS1 OE_0** DIF_0 DIF_0# VDD DIF_1 DIF_1# OE_1* VDD GND OE_2* DIF_2 DIF_2# VDD DIF_3 DIF_3# OE_3** SEL14M_25M# SPREAD DIF_STOP#
Note: Pin names followed by '**' have 120 Kohm pull DOWN resistors Pin names followed by an '*' have 120 Kohm pull UP resistors
48-pin SSOP & TSSOP
0823--04/02/04 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. Third party brands and names are the property of their respective owners
ICS9FG108
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XIN/CLKIN X2 VDD GND REFOUT FS2 OE_7** DIF_7 DIF_7# VDD DIF_6 DIF_6# OE_6* VDD GND OE_5* DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4** SDATA SCLK PIN TYPE IN OUT PWR PWR IN IN IN OUT OUT PWR OUT OUT IN PWR PWR IN OUT OUT PWR OUT OUT IN I/O IN DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Reference Clock output Frequency select pin. Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Power supply, nominal 3.3V Ground pin. Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant.
Note: Pin names followed by '**' have 120 Kohm pull DOWN resistors Pin names followed by '*' have 120 Kohm pull UP resistors
0823--04/02/04
2
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
Pin Description (Continued)
PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PIN NAME DIF_STOP# SPREAD SEL14M_25M# OE_3** DIF_3# DIF_3 VDD DIF_2# DIF_2 OE_2* GND VDD OE_1* DIF_1# DIF_1 VDD DIF_0# DIF_0 OE_0** FS1 FS0 IREF PIN TYPE IN IN IN IN OUT OUT PWR OUT OUT IN PWR PWR IN OUT OUT PWR OUT OUT IN IN IN OUT PWR PWR DESCRIPTION Active low input to stop differential output clocks. Asynchronous, active high input to enable spread spectrum functionality. Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Ground pin. Power supply, nominal 3.3V Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Frequency select pin. Frequency select pin. This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
47 GNDA 48 VDDA Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors Pin names followed by '*' have 120 Kohm pull UP resistors
0823--04/02/04
3
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
General Description
ICS9FG108 is a Frequency Timing Generator that provides 8 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps. ICS9FG108 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus control.
Block Diagram
XIN/CLKIN OSC X2 OE(7:0)
R EF OU T
PROGRAMMABLE SPREAD PLL
STOP LOGIC
4 DIF(7:0)
SPREAD SEL14M_25M# DIF_STOP# FS(2:0) SDATA SCLK CONTROL LOGIC
IREF
Power Groups
Pin Number VDD GND 3 4 10,14,19,31,36,40 15,35 N/A 47 48 47 Description REFOUT, Digital Inputs, SMBus DIF Outputs IREF Analog VDD & GND for PLL Core
0823--04/02/04
4
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL V IH V IL I IH IIL1 Input Low Current IIL2 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization to 1st clock Triangular Modulation DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD MIN 2 VSS - 0.3 -5 -5 -200 250 200 14 1.5 25 7 5 6 1.8 30 40 10 5 TYP MAX VDD + 0.3 0.8 5 UNITS NOTES V V uA uA uA mA mA MHz nH pF pF ms kHz ns ns 3 1 1 1 1,2 1 1 1
Operating Supply Current Input Frequency 3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 Modulation Frequency DIF output enable Input Rise and Fall times
1 2
IDD3.3OP Fi Lpin CIN COUT TSTAB fMOD tDIFOE tR/tF
Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet ppm frequency accuracy on PLL outputs.
0823--04/02/04
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Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 850 mV 150 1150 550 140 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1 1,2 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1 2
tr tf d-tr d-tf dt3 tsk3 t jcyc-cyc
700 700 125 125 55 50 50
Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom
45
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
3
Figures are for down spread.
0823--04/02/04
6
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) SYMBO PARAMETER CONDITIONS MIN TYP MAX UNITS Notes L Long Accuracy ppm see Tperiod min-max values -300 0 300 ppm 1 14.318MHz output nominal 69.8270 69.8413 69.8550 ns 1,2 Clock period Tperiod Clock period Tperiod 25.000MHz output nominal 39.9880 40.0000 40.0120 ns 1,2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 VOH @MIN = 1.0 V, -29 -23 mA 1 Output High Current I OH VOH@MAX = 3.135 V VOL @MIN = 1.95 V, Output Low Current I OL 29 27 mA 1 VOL @MAX = 0.4 V Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 1.6 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 1.6 2 ns 1 Duty Cycle Jitter
1 2
dt1 tjcyc-cyc
VT = 1.5 V VT = 1.5 V
45 150
55 200
% ps
1 1
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or 25.00 MHz
0823--04/02/04
7
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
I C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Control Pin # Name Type 0 1 Byte 0 Function RW 27 Bit 7 FS31 5 See Frequency RW Bit 6 FS21 1 Selection Table, Page 1 RW 44 Bit 5 FS1 RW 7 Bit 4 FS01 1 26 RW Off On Bit 3 Spread Enable Enable Software Control of Frequency, Spread Enable Hardware Software RW Bit 2 (Spread Type always Software Select Select Control) Bit 1 Bit 0 DIF_STOP# drive mode SPREAD TYPE RW RW Driven Down Hi-Z Center
2
PWD Pin 27 Pin 5 Pin 44 Pin 7 Pin 26
0
0 0
Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. I C Table: Output Enable Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
2
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Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
I C Table: Output Stop Mode Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Free-run Free-run Free-run Free-run Free-run Free-run Free-run Free-run 1 Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able PWD 0 0 0 0 0 0 0 0
2
I C Table: Frequency Select Readback Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 27 6 44 45 26 Pin # Name Control Function Type R R R R R R R R See Frequency Selection Table, Page 1 0 1 PWD Pin 27 Pin 6 Pin 44 Pin 45 Pin 26 X X X
2
SEL14M_25M#1 State of pin 27 (FS3) State of pin 6 FS21 1 State of pin 44 FS1 State of pin 45 FS01 State of pin 26 SPREAD1 RESERVED RESERVED RESERVED
Off On RESERVED RESERVED RESERVED
Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not.
0823--04/02/04
9
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
I C Table: Vendor & Revision ID Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD 0 0 0 0 0 0 0 1
2
VENDOR ID
I C Table: DEVICE ID Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Type R R R R R R R R 0 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED PWD 0 0 0 0 1 0 0 0
2
Device ID = 08 hex
I C Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 1 1 1
2
0823--04/02/04
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Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the I2C DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the I2C DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# DIF DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 10nS of DIF_Stop# de-assertion to a voltage greater than 200mV.
DIF_Stop# DIF DIF#
DIF Internal
Tdrive_DIF_Stop, 10nS >200mV
0823--04/02/04
11
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
Ordering Information
ICS9FG108yFLF-T
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging Lead Free (if required) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0823--04/02/04
12
Integrated Circuit Systems, Inc.
ICS9FG108 Advance Information
N
c
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil)
L
(20 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL A A1 A2 b c D E E1 e L N a aaa
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
-Ce
b SEATING PLANE
VARIATIONS N 48 D mm. MIN 12.40 MAX 12.60 MIN .488 D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9FG108yGLF-T
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging Lead Free (if required) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0823--04/02/04
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